1. Field of the Invention
The invention relates to the forming of polycrystalline silicon patterns such as those employed in MOS silicon gate transistors.
2. Prior Art
In the fabrication of integrated circuits, particularly metal-oxide-semiconductor (MOS) circuits employing polycrystalline silicon gates, a silicon layer is etched to form gates or other circuit elements such as interconnecting lines, capacitors, and others. Generally, a masking layer or member (typically an oxide or nitride layer) is defined in a predetermined pattern by photolithographic techniques on a polycrystalline silicon layer. Then, the polycrystalline silicon layer is subjected to a silicon etchant, for example, by dipping the substrate in an etchant or through use of a plasma, to remove the regions of the silicon layer not protected by the masking member. This etching process is not self-limiting, and results in uncontrolled undercutting, which shall be discussed in more detail in conjunction with FIG. 1. Moreover, with this prior art etching process, only a few wafers may be etched at one time, and even then, the etching is not always uniform across a given wafer, or from wafer-to-wafer. In contrast with the present invention, there is a controlled shift in the critical dimensions from the masking member to the final silicon pattern.
Typically, in the fabrication of silicon gates for field-effect transistors, gate widths of 6.+-. 1 micron are obtainable. The performance of MOS field-effect transistors may be improved by reducing the width of these gates; this reduction provides a better speed/power product, and also permits fabrication of denser arrays. However, this critical gate width is limited by the accuracy obtainable from the etching process, and other parameters used to define the gate. With the prior art etching process, primarily because of the uncontrolled undercutting, it is difficult to reduce this critical gate width in production processing.
Narrower channel widths in field-effect transistors have been obtained through the use of lateral diffusion. For example, an an n-type (phosphorous) source region and drain region are typically formed in alignment with a gate. Through lateral diffusion from these regions, the channel width is reduced. However, the advantages gained by this narrower channel, to some extent, are offset by the increase in gate-to-source and gate-to-drain capacitance. This increase capacitance, particularly the Miller capacitance caused by the overlapping of the gate and drain region, reduces the speed of the transistor.